1. Field of the Invention
This application relates generally to frequency synthesizers. More specifically, the application describes a novel direct digital frequency synthesizer (DDFS), and a hybrid frequency synthesizer combining a novel DDFS and a phase locked loop (PLL).
2. Description of the Related Art
The frequency synthesizer is an important element of a wireless device. It controls the frequency of transmission and reception, and should, therefore, generate an output signal with an accurate frequency which has low spurious levels, low phase noise, and good frequency resolution. In addition, the compact nature of modem mobile devices creates a need for frequency synthesizers which have low power consumption, require few external components, and occupy very little space.
In many mobile devices, frequency synthesizers are also used to modulate the transmission signal. With a rising demand for systems capable of complex modulation schemes such as Quadrature Amplitude Modulation (QAM) or Quaternary Phase Shift Keying (QPSK), there is a need for frequency synthesizers which have very high switching speeds and which are capable of performing complex modulations and compressing high data rates into a narrow RF spectrum.
Two circuits commonly used for frequency synthesis are the phase locked loop frequency synthesizer (PLL) and the direct digital frequency synthesizer (DDFS). FIG. 1 sets forth a block diagram of a known phase locked loop frequency synthesizer. In this circuit, the free running frequency of the voltage controlled oscillator (VCO) 18 is divided by a factor of N in a divider 20, and compared with a reference input frequency (Fref) by a phase detector 12. The phase detector 12 generates an error signal which controls the direction of a current pulse generated by a charge pump 14 based on the phase difference between Fref and the feedback signal. A loop filter 16 then converts the current pulse from the charge pump 14 into a DC voltage which controls the frequency of the VCO output. When the loop is locked, Fout is equal to N*Fref.
Although the PLL shown in FIG. 1 is useful for generating high frequencies locked to a reference frequency, its use in high performance mobile devices is limited because of its slow switching speed, relatively large step size (equal to Fref) and spurious output. In addition, because the PLL has a fixed input (Fref), its output signal frequency can only be changed by changing the division ratio N. This feature limits the utility of such PLLs in mobile systems having complex modulation schemes.
FIG. 2 shows a block diagram of a known direct digital frequency synthesizer (DDFS). In this circuit, a reference frequency (Fref) is used by a phase accumulator 24 to generate a discrete phase signal having phase increments controlled by a frequency control word (FCW) input to the phase accumulator 24. Since the phase accumulator 24 has fixed output word length, the accumulated phase value will eventually overflow, such that the discrete phase signal is a substantially periodic signal having a period T as shown in FIG. 2. The discrete phase signal is then used to address a sine lookup ROM 26, which generates a discrete waveform having a frequency equal to the inverse of the discrete phase signal period (1/T). The discrete waveform is converted to a continuous waveform by a digital to analog converter (DAC) 28, and is smoothed by a deglitcher 30 and low pass filter 32.
This known DDFS 22 has a high switching speed and can be used for accurate modulation. Its utility in high performance systems is limited, however, due to its spurious output and large power consumption at high frequencies. The spurious output associated with DDFS 22 is caused by the non-linear nature of the DAC 28, and the finite word length effects in the sine lookup ROM 26 and DAC 28. The location and level of these spurious signals have been analyzed in xe2x80x9cAn analysis of the output Spectrum of Direct Digital Frequency Synthesizers in the presence of Phase Accumulator Truncation,xe2x80x9d Henry T. Nicholas, and Henry Samueli, 41stAnnual Frequency Control Symposium, 1987, xe2x80x9cThe Optimization of Direct Digital Frequency Synthesizer Performance in the presence of Finite Word Length Effects,xe2x80x9d Henry T. Nicholas, Henry Samueli, and Bruce Kin, 42nd Annual Frequency Control Symposium, 1988, pp 357-363, and xe2x80x9cAn Exact Spectral Analysis of a Number Controlled Oscillator Based Synthesizer,xe2x80x9d Joseph F. Garvey, Daniel Babitch, 44th Annual Frequency Control Symposium, 1990, pp 511-521. It has been shown that the dominant component of the spurious content is due to the phase errors introduced by phase truncation at the output of the phase accumulator 24.
In addition, the maximum frequency that can be directly generated from the DDFS 22 shown in FIG. 2 is equal to one half the reference frequency (Fref/2). Practically, only 30% of Fref can be generated. Consequently, in a system requiring frequencies on the order of tens or hundreds of MHz, the reference frequency must be very high. The power consumption necessary to generate the required reference frequency makes it difficult to integrate this known DDFS 22 into most next generation mobile devices.
FIG. 3 shows a block diagram of a known hybrid frequency synthesizer 34. This hybrid circuit 34 combines the DDFS 22 shown in FIG. 2 with the PLL 10 shown in FIG. 1. The PLL 10 in this circuit uses the lower frequency output of the DDFS 22 as its reference frequency, and converts it into a higher frequency output signal suitable for use in mobile devices. This hybrid combination 34 resolves some of the problems associated with the synthesizers shown in FIG. 1 and FIG. 2. Nonetheless, this known hybrid 34 is unsuitable for many high performance mobile applications because of its large power consumption and spurious output. In order to increase the output of the DDFS 22 to a frequency in the RF range, the PLL 10 must have a large division ratio N. The cost of a large division ratio N is that the spurious signals generated by the DDFS 22 are exponentially increased in strength by the PLL 10 and passed through to the frequency synthesizer output. Moreover, the DDFS 22 cannot generate an output with acceptably low spurious signals without utilizing a very high reference frequency on the order of hundreds of MHz. This requires an unacceptable trade-off between power consumption and signal integrity.
Briefly stated, the relatively high power consumption and output noise associated with known frequency synthesis techniques limit their application in power and noise sensitive environments, such as mobile communications systems. Moreover, most current research in frequency synthesizer design is focused on obtaining higher frequencies, close to 1 GHz, directly from a DDFS. Unfortunately, circuits of this type require clock frequencies of 2 GHz and higher, and, therefore, exhibit power consumption on the order of Watts. This direct synthesis approach is not feasible in portable wireless applications where battery life and power consumption are critical parameters.
A direct digital frequency synthesizer and a hybrid frequency synthesizer combining the direct digital frequency synthesizer and a phase locked loop is provided. The direct digital frequency synthesizer includes a phase accumulator that is configured to generate a discrete phase signal. Spurious phase modulation in the discrete phase signal is reduced by a noise shaper, and the output of the noise shaper is then used to address a phase-to-amplitude translator. The phase-to-amplitude translator generates a discrete waveform which is converted to a continuous waveform by a digital to analog converter. The hybrid frequency synthesizer uses a mixer to combine a reference frequency generated by a reference source and a DDFS output signal generated by a direct digital frequency synthesizer. The output from the mixer is then coupled to the input of a phase locked loop which multiplies the mixer output to generate the frequency synthesizer output.